An important aim of ongoing research in the semiconductor industry is increasing semiconductor performance while decreasing the size of semiconductor devices. One known step the industry has taken to attain this increased semiconductor performance is to implement strained silicon technology. Fortunately, strained silicon technology allows for the formation of higher speed devices. For example, as the electrons in the strained silicon experience less resistance and flow up to 80% faster than in unstrained silicon, the introduction of the strained silicon layer allows for the formation of higher speed devices.
Strained-silicon transistors may be created a number of different ways. In one instance strained layers are created by forming a layer of silicon germanium (SiGe) over or below a silicon epitaxial layer. The average distance between atoms in the SiGe crystal lattice is greater than the average distance between atoms in an ordinary silicon lattice. Because there is a natural tendency of atoms inside different crystals to align with one another when a second crystal is formed over a first crystal, when silicon is deposited on top of SiGe, or vice-versa, the silicon crystal lattice tends to stretch or “strain” to align the silicon atoms with the atoms in the SiGe layer. Unfortunately, the use of the SiGe layer is difficult and costly to implement.
In another instance, strained layers are created by a layer of dislocation loops. The insertion of an extra plane of atoms (a dislocation loop) in an ordinary silicon lattice creates stress in the surrounding silicon lattice. Currently, the layer of dislocation loops are introduced by implanting a dopant species into the substrate, thereby creating the strain. Currently, these dislocation loops are positioned below the channel region of the device or below the source/drain regions of the device to introduce the required strain. It is believed that the dislocation loops are currently placed deep below the channel region or source/drain regions so as not to interfere with channel mobility and source/drain junctions, respectively. Unfortunately, the placement of the dislocation loops makes it difficult to achieve the requisite amount of strain.
In another instance, a strained layer may be formed on the gate structure to generate strain in the channel region. Unfortunately, limitations on the strained layer thickness limits the amount of strain that can be introduced into the channel region.
Accordingly, what is needed in the art is a semiconductor device and method of manufacture therefore that experiences the benefits of a strained silicon layer without experiencing the aforementioned drawbacks.